Order the sequence of FDE Cycle
ALU executes the instructions if instruction is to perform arithmetic or logical or comparison operation. I/O ( input and output) instructions are executed by the I/O devices.
Instructions to be executed are fetched by the buses from the RAM and stored in Registers in the processor
Instruction in CIR is decoded by the control unit and signal are sent to execute the instruction
Below are the steps that how instructions/ data is fetched from the processor. They are out of order, list them in order
Program counter (PC) holds address of the instruction to be fetched from the RAM
PC is incremented to the address of the next instruction to be fetched
Instruction in MDR is sent to CIR via data bus
The instruction/ data is fetched from address in memory and send to MDR using data bus
Address in PC is sent to the MAR via address bus
What is an interrupt in computer science?
What happens when a processor receives an interrupt signal?
What could cause an interrupt signal?
Order the steps when interrupt is detected how is it serviced
Otherwise load data from stack and continue with process
Priority is checked If lower priority than current process continue with F-E cycle
Location / type of interrupt identified...
If higher priority than current process …state of current process is / registers are stored on stack
appropriate ISR is called to handle the interrupt
When ISR finished, check for further interrupts (of high priority) / return to step 1
Interrupt is detected only at at the start of the FDE cycle