FDE and Processor Performance

Order the sequence of FDE Cycle

1. ALU executes the instructions if instruction is to perform arithmetic or logical or comparison operation. I/O ( input and output) instructions are executed by the I/O devices.
2. Instructions to be executed are fetched by the buses from the RAM and stored in Registers in the processor
3. Instruction in CIR is decoded by the control unit and signal are sent to execute the instruction

Below are the steps that how instructions/ data is fetched from the processor. They are out of order, list them in order

1. The instruction/ data is fetched from address in memory and send to MDR using data bus
2. PC is incremented to the address of the next instruction to be fetched
3. Address in PC is sent to the MAR via address bus  ​
4. Program counter (PC) holds address of the instruction to be fetched from the RAM
5. Instruction in MDR is sent to CIR via data bus

What is an interrupt in computer science?

What happens when a processor receives an interrupt signal?

What could cause an interrupt signal?

Order the steps when interrupt is detected how is it serviced

1. When ISR finished, check for further interrupts (of high priority) / return to step 1
2. If higher priority than current process …state of current process is / registers are stored on stack
3. Location / type of interrupt identified...
4. Priority is checked If lower priority than current process continue with F-E cycle
5. appropriate ISR is called to handle the interrupt
6. Otherwise load data from stack and continue with process

Interrupt is detected only at at the start of the FDE cycle